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d 1 s 1 wr dual-in-line in 1 nc v nc gnd nc v l nc v+ rs in 2 d 2 s 2
dg421 dg425 d 1 s 1 wr dual-in-line in 1 d 3 v s 3 gnd s 4 v l d 4 v+ rs in 2 d 2 s 2
dg421/423/425 siliconix s-52880erev. d, 28-apr-97 1 low-power, high-speed, latchable cmos analog switches features benefits applications latched control inputs rail-to-rail analog input range on-resistance: 25 fast switching actionet on : 170 ns micropower requirementsep d : 35 nw ttl and cmos logic compatible low leakage: 40 pa p compatible wide dynamic range reduced component count low signal errors and distortion break-before-make switching action battery-compatible operation data bus switching sample-and-hold circuits programmable filters p controlled analog systems portable instruments telecommunication systems description the dg421/423/425 are monolithic analog switches featuring latchable logic inputs to simplify interfacing with microprocessors. this series combines fast switching speed (t on : 170 ns, typ), and low on-resistance (r ds(on) : 25 , typ) making it ideally suited for battery powered industrial and military applications that require microprocessor compatible analog switches. the dg421 has two normally open switches (spst). the dg423 has two single-pole, double-throw (spdt) pairs. the dg425 has two normally open pairs (dpst). to achieve high-voltage ratings and superior switching performance, the dg421 series is built on siliconix's high voltage silicon gate cmos process. break-before-make is guaranteed for the dg423. an epitaxial layer prevents latchup. each switch conducts equally well in both directions when on and blocks input voltages up to the supply rail voltages when off. the input data latches become transparent when wr is set low. when wr goes high the latches store the logic control data. a low on rs resets all switches to their default state (all inputs low). functional block diagram and pin configuration truth table dg421/dg425 wr rs in x switch 0 1 0 off 1 on logic a0o 0.8 v logic a1o 2.4 v updates to this data sheet may be obtained via facsimile by calling siliconix faxback, 1-408-970-5600. please request faxback document #70052.
dg421/423/425 2 siliconix s-52880erev. d, 28-apr-97 functional block diagram and pin configuration (cont'd) plcc

d 3 v s 3 gnd nc nc s 4 v l d 4 v+ dg423 d 1 s 1 wr dual-in-line in 1 d 3 v s 3 gnd s 4 v l d 4 v+ rs in 2 d 2 s 2
dg423 truth table dg423 wr rs in x sw 1 , sw 2 sw 3 , sw 4 logic a 0 o 08v 0 1 0 off on logic 0 0 . 8 v logic a1o 2.4 v 1 on off ordering information dg421/423/425 temp range package part number dg421dj 40 to 85 16-pin plastic dip dg423dj 40 to 85 dg425dj 20-pin plcc DG423DN latch operation truth table in x rs wr latch/switch x x 1 0 transparent latch operation x 1 control data latched-in, switches on or off as selected by last in x x 0 x all latches reset, switches on or off as x x when in x = 0, wr = 0, rs = 1 absolute maximum ratings voltages referenced to v v+ 44 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . gnd 25 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v l (gnd 0.3 v) to (v+) +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . digital inputs a v s , v d v minus 2 v to (v+ plus 2 v) . . . . . . . . . . . . or 30 ma, whichever occurs first continuous current (any terminal) 40 ma . . . . . . . . . . . . . . . . . . . . . current, s or d (pulsed 1 ms, 10% duty) 100 ma . . . . . . . . . . . . . . . . . storage temperature 65 to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . power dissipation (package) b 16-pin plastic dip c 470 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20-pin plcc d 800 mw . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . notes: a. signals on s x , d x , or in x exceeding v+ or v will be clamped by internal diodes. limit forward diode current to maximum current ratings. b. all leads welded or soldered to pc board. c. derate 6 mw/ c above 75 c d. derate 10 mw/ c above 75 c
dg421/423/425 siliconix s-52880erev. d, 28-apr-97 3 specifications test conditions unless otherwise specified d suffix 40 to 85 c parameter symbol v+ = 15 v, v = 15 v v l = 5 v, v in = 2.4 v, 0.8 v e temp a min c typ b max c unit analog switch analog signal range d v analog full 15 15 v drain-source on-resistance r ds(on) i s = 10 ma, v d = 8.5 v v+ = 13.5 v, v = 13.5 v room full 25 35 45 switch off leakage current i s(off) v+ = 16.5 v, v = 16.5 v room full 0.25 5 0.01 0.25 5 i d(off) v d = 15.5 v, v s = 15.5 v room full 0.25 5 0.01 0.25 5 na channel on leakage current i d(on) v+ = 16.5 v, v = 16.5 v room full 0.4 10 0.04 0.4 10 digital control input current with v in low i il v in under test = 0.8 v, all other = 2.4 v full 0.5 0.005 0.5 a input current with v in high i ih v in under test = 2.4 v, all other = 0.8 v full 0.5 0.005 0.5 a dynamic characteristics turn-on time t on r l = 300 , c l = 35 pf sfi 2 room full 170 250 300 turn-off time t off see figure 2 room full 140 200 200 t ww room full 200 200 ns latch timing t dw r l = 300 , c l = 35 pf v s = 10 v room full 100 100 ns t wd room full 60 100 break-before-make time delay t d dg423 only, r l = 300 , c l = 35 pf see figure 3 room 5 25 charge injection d q c l = 10 nf, v gen = 0 v, r gen = 0 see figure 4 room 60 pc off isolation reject ratio oirr r l = 50 , c l = 5 pf, f = 1 mhz room 65 crosstalk (channel-to-channel) x talk between any two channels r l = 50 , c l = 5 pf, f = 1 mhz room 76 db source off capacitance c s(off) full 9 drain off capacitance c d(off) f = 1 mhz full 9 pf channel on capacitance c d(on) full 35 power supply positive supply current i+ room full 0.0001 1 5 negative supply current i v+ = 16.5 v, v = 16.5 v room full 1 5 0.0001 a logic supply current i l v in = 0 or 5 v room full 0.0001 1 5 a ground current i gnd room full 1 5 0.0001 notes: a. room = 25 c, full = as determined by the operating temperature suffix. b. typical values are for design aid only, not guaranteed nor subject to production testing. c. the algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data s heet. d. guaranteed by design, not subject to production test. e. v in = input voltage to perform proper function.
dg421/423/425 4 siliconix s-52880erev. d, 28-apr-97 typical characteristics r ds(on) vs. v d and power supply voltage r ds(on) vs. v d and power supply voltage input switching theshold vs. v+ and v supply voltages leakage currents vs. analog voltage supply currents vs. switching frequency v d drain voltage (v) v d drain voltage (v) v analog analog voltage (v) f frequency (hz) v+, v positive and negative supplies (v) r ds(on) drain-source on-resistance ( (pa) i , i sd i+, i (ma) (v) t v r ds(on) drain-source on-resistance ( 50 20 10 0 10 20 40 30 20 10 15 5 5 15 5 v t a = 25 c 7.5 v 10 v 15 v 20 v 70 0 5 10 15 20 60 50 40 30 20 t a = 25 c v = 0 v v+ = 7.5 v 10 v 15 v 20 v 15 0 10 5 0 5 10 15 50 100 150 i d(on) i d(off) or i s(off) 2.5 0 2.0 1.5 1.0 0.5 0 5 10 15 20 4 3 2 1 i+, i 1 k 10 k 100 k 1 m 0
dg421/423/425 siliconix s-52880erev. d, 28-apr-97 5 schematic diagram (typical channel) figure 1. s d v v+ latch v+ v l in x wr v level shift/ drive rs test circuits figure 2. switching time 0 v logic input switch input* switch output 3 v 0 v switch input* v s t r <20 ns t f <20 ns 90% v s t off t on v o 90% v o *v s = 10 v for t on , v s = 10 v for t off note: logic input waveform is inverted for switches that have the opposite logic sense control c l (includes fixture and stray capacitance) v+ in r l r l + r ds(on) v o = v s s d 15 v v o gnd 10 v v l c l 35 pf v r l 300 +15 v +5 v 50% rs wr
dg421/423/425 6 siliconix s-52880erev. d, 28-apr-97 test circuits (cont'd) figure 3. break-before-make off on on in v o v o q = v o x c l c l 10 nf d r g v o v+ s v 3 v in v l v g 15 v +15 v +5 v figure 4. charge injection 0 v logic input switch 1 switch 2 output 3 v 50% 0 v output 0 v 90% v o2 v o1 90% t d t d v o2 c l (includes fixture and stray capacitance) v+ r l1 300 s 2 c l1 35 pf v s 1 v l 10 v in d 2 10 v d 1 v o1 15 v gnd +5 v +15 v r l2 300 c l2 35 pf rs wr gnd, wr rs figure 5. crosstalk figure 6. off isolation v s v+ s r l in v o 0v, 2.4 v off isolation = 20 log v s v o 15 v gnd v l v c r g = 50 d +5 v +15 v c rs wr 0v, 2.4 v s 1 x talk isolation = 20 log v s v o d 2 c = rf bypass r l d 1 s 2 v s 0v, 2.4 v in 1 50 v o in 2 r g = 50 v l v+ 15 v gnd v nc c +15 v c +5 v c rs wr c
dg421/423/425 siliconix s-52880erev. d, 28-apr-97 7 test circuits (cont'd) figure 7. source/drain capacitances figure 8. latch timing d in s v l v+ 15 v gnd v c 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent +5 v +15 v c wr rs 3 v 0 3 v 0 50% 20% 80% 3 v 0 0 50% switch output v o rs wr in x t ww t dw t wd t off(rs) t rs 80% c applications figure 9 shows a circuit configured to increase the effective resolution of the 12-bit dac to 13 bits. the circuit operates with a sign plus magnitude code. a sign bit of a0o connects r 3 to gnd, giving 12-bit resolution per quadrant. 12-bit plus sign magnitude code table sign digital input analog output g bit msb lsb gp (v out) 0 1111 1111 1111 +(4095/4096)v in 0 0000 0000 0000 0 v 1 0000 0000 0000 0 v 1 1111 1111 1111 +(4095/4096)v in 12 dg423 13 + analog common sign bit 20 k 20 k 10 k cs in 1 v in v out wr r 1 r 2 r 4 r 5 r 3 a 2 a 1 + wr c l 33 pf out agnd d b11 d b0 v ref v dd v dd r fb figure 9. 12-bit plus sign magnitude d/a converter
+ + + mic a dg425 mic b v out d 1 d 0 wr rs 500 500 500 500 500 500 figure 11. bus-controlled selector for balanced-line microphones dg421/423/425 8 siliconix s-52880erev. d, 28-apr-97 applications when switch s 1 of figure 10 is closed, the op amp is placed in the familiar unity-gain non-inverting configuration. when switch s 2 is closed and s 1 is open the gain is given by: the microprocessor system wr must gate the decoder output to ensure proper timing. figure 11 shows a balanced-line microphone input stage that provides selection or summing between two balanced-line microphones and also performs differential-to-single-ended conversion. either mic a or mic b can be selected, and neither and/or both may be summed at the output. this configuration uses avirtual groundo switching, a method which minimizes distortion resulting from the analog switch on-resistance modulation. the actual voltage swings experienced by the analog switch barely exceed 1 v for a 15-v full-scale range input. v+ v 15 v +15 v + address decoder data bus dg421 system wr wr v in v out d 1 d 0 rs v l r 1 r 2 74hc138 figure 10. bus-controlled precision gain-ranging circuit gnd +5 v d 1 d 2 output 0 0 none 0 1 mic a 1 0 mic b 1 1 mic a and mic b

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